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ad7864 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2004 analog devices, inc. all rights reserved. 4-channel, simultaneous sampling, high speed, 12-bit adc functional block diagram stby frstdata int/ext clock select output data registers 2.5v reference signal scaling v in1a v in1b v in2a v in2b v in3a v in3b v in4a v in4b busy signal scaling signal scaling signal scaling track/hold 4 eoc wr cs db0 db11 rd agnd dgnd v drive dv dd v ref gnd v ref av dd 6k ad7864 12-bit adc software latch conversion control logic mux convst sl1 sl2 sl3 sl4 h /s sel clkin int /ext clk agnd agnd int clock db0 to db3 features high speed (1.65 s) 12-bit adc 4 simultaneously sampled inputs 4 track/hold amplifiers 0.35 s track/hold acquisition time 1.65 s conversion time per channel hw/sw select of channel sequence for conversion single-supply operation selection of input ranges: 10 v, 5 v for ad7864-1 2.5 v for ad7864-3 0 v to 2.5 v, 0 v to 5 v for ad7864-2 high speed parallel interface that allows interfacing to 3 v processors low power, 90 mw typ power saving mode, 20 w typ overvoltage protection on analog inputs applications ac motor control uninterrupted power supplies data acquisition systems communications general description the ad7864 is a high speed, low power, 4-channel simulta- neous sampling 12-bit a/d converter that operates from a single 5v supply. the part contains a 1.65 m s successive approxima- tion adc, four track/hold amplifiers, a 2.5 v reference, an on-chip clock oscillator, signal conditioning circuitry, and a high speed p arallel interface. the input signals on four channels are sam pled simultaneously, thus preserving the relative phase information of the signals on the four analog inputs. the part accepts analog input ranges of 10 v, 5 v (ad7864-1), 0 v to +2.5 v, 0 v to +5 v (ad7864-2), and 2.5 v (ad7864-3). the part allows any subset of the four channels to be converted in order to maximize the throughput rate on the selected sequence. the channels to be converted can be selected via hardware (channel select input pins) or software (programming the channel select register). a single conversion start signal ( convst ) simultaneously places all the track/holds into hold and initiates a conversion se que nc e for the selected channels. the eoc signal indicates the end of each individual conversion in the selected conversion sequence. the busy signal indicates the end of the conver- sion sequence. d ata is read from the part by means of a 12-bit parallel data bus using the standard cs and rd signals. maximum through- p ut for a single channel is 500 ksps. for all four channels, the maximum throughput is 130 ksps for the read during conver- sion sequence operation. the throughput rate for the read after conversion sequence operation depends on the read cycle time of the processor. see the timing and control section. the ad7864 is available in a small (0.3 sq. inch area) 44-lead mqfp. product highlights 1. the ad7864 features four track/hold amplifiers and a fast (1.65 m s) adc allowing simultaneous sampling and then conversion of any subset of the four channels. 2. t he ad7864 operates from a single 5 v supply and consumes only 90 mw typ, making it ideal for low power and portable applications. also see the standby mode operation section. 3. the part offers a high speed parallel interface for easy con- nection to microprocessors, microcontrollers, and digital signal processors. 4. the part is offered in three versions with different analog input ranges. the ad7864-1 offers the standard industrial input ranges of 10 v and 5 v; the ad7864-3 offers the common signal processing input range of 2.5 v; the ad7864-2 can be used in unipolar 0 v to 2.5 v, 0 v to 5 v applications. 5. the part features very tight aperture delay matching between the four input sample-and-hold amplifiers.
e2e rev. b ad7864especifications (v dd = 5 v 5%, agnd = dgnd = 0 v, v ref = internal, clock = internal; all specifi- cations t min to t max , unless otherwise noted.) parameter a version 1 b version unit test conditions/comments sample and hold C C C C C C C C C C C
e3e rev. b ad7864 parameter a version 1 b version unit test conditions/comments logic inputs input high voltage, v inh 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 m a max input capacitance, c in 4 10 10 pf max logic outputs output high voltage, v oh 4.0 4.0 v min i source = 400 m a output low voltage, v ol 0.4 0.4 v max i sink = 1.6 ma db11 to db0 high impedance leakage current 10 10 m a max capacitance 4 10 10 pf max output coding ad7864-1, ad7864-3 twos complement ad7864-2 straight (natural) binary conversion rate conversion time 1.65 1.65 m s max for one channel track/hold acquisition time 2, 3 0.35 0.35 m s max throughput time 130 130 ksps max for all four channels power requirements v dd 55 v nom 5% for specified performance i dd (5 m a typ) logic inputs = 0 v or v dd normal mode 24 24 ma max standby mode 20 20 m a max typically 4 m a power dissipation normal mode 120 120 mw max typically 90 mw standby mode 100 100 m w max typically 20 m w notes 1 temperature ranges are as follows: a, b versions: C
ad7864 e4e rev. b timing characteristics 1, 2 parameter a, b versions unit test conditions/comments t conv 1.65 m s max conversion time, internal clock 13 clock cycles conversion time, external clock 2.6 m s max clkin = 5 mhz t acq 0.34 m s max acquisition time t busy no. of channels selected number of channels multiplied by (t conv + t 9 ) C
ad7864 e5e rev. b absolute maximum ratings * (t a = 25 C C C C C C C C C C C C C C C C C C C C C C
ad7864 e6e rev. b pin function descriptions pin no. mnemonic description 1 busy busy output. the busy output is triggered high by the rising edge of convst and remains high until conversion is completed on all selected channels. 2 frstdata first data output. frstdata is a logic output which, when high, indicates that the output data register pointer is addressing register 1
ad7864 e7e rev. b terminology signal-to-(noise + distortion) ratio this is the measured ratio of signal-to-(noise + distortion) at the output of the a/d converter. the signal is the rms amplitude of the fundamental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio depends on the number of quantization levels in the digitization process; the more levels, the smaller the quan tization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal-to -( noise + distortion ) = (6.02 n + 1.76) db thus, for a 12-bit converter, this is 74 db. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamen- tal. for the ad7864, it is defined as thd vvvvv v 23456 1 () 22222 db = ++++ 20log where v 1 is the rms amplitude of the fundamental, and v 2 , v 3 , v 4 , v 5 , a nd v 6 are the rms amplitudes of the second through the fifth harmonics. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it is a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion prod- ucts at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3, and so on. intermodulation terms are those for w hich neither m nor n are equal to zero. for example, the second-order terms include (fa + fb) and (fa C C C C C C C C C C C C
ad7864 e8e rev. b converter details the ad7864 is a high speed, low power, 4-channel simulta- neous sampling 12-bit a/d converter that operates from a single 5v supply. the part contains a 1.65 m s successive approximation adc, four track/hold amplifiers, an internal 2.5 v reference, and a high speed parallel interface. there are four analog inputs that can be simultaneously sampled, thus preserving the relative phase information of the signals on all four analog inputs. thereafter, conversions will be completed on the selected subset of the four channels. the part accepts an analog input range of 10 v or 5v (ad7864-1), 2.5 v (ad7864-3), and 0 v to +2.5 v or 0 v to +5 v (ad7864-2). overvoltage protection on the analog inputs of the part allows the input voltage to go to 20 v, (ad7864-1 10 v range), C C C
ad7864 e9e rev. b ad7864-1 figure 2 shows the analog input section of the ad7864-1. each input can be configured for 5 v or 10 v operation on the ad7864-1. for 5 v (ad7864-1) operation, the v inxa and v inxb inputs are tied together and the input voltage is applied to both. for 10 v (ad7864-1) operation, the v inxb input is tied to agnd and the input voltage is applied to the v inxa input. the v inxa and v inxb inputs are symmetrical and fully inter- changeable. thus for ease of pcb layout on the 10 v range, the input voltage may be applied to the v inxb input while the v inxa input is tied to agnd. 2.5v reference t/h to adc reference circuitry 6k r2 r3 to internal comparator ad7864-1 r1 r4 agnd v in1b v in1a v ref figure 2. ad7864-1 analog input structure for the ad7864-1, r1 = 6 k w , r2 = 24 k w, r3 = 24 k w , and r4 = 12 k w . the resistor input stage is followed by the high input impedance stage of the track/hold amplifier. the designed code transitions take place midway between suc- cessive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs, etc.). lsb size is given by the formula 1 lsb = fsr/4096. for the 5 v range, 1 lsb = 10 v/4096 = 2.44 mv. for the 10 v range, 1 lsb = 20 v/4096 = 4.88 mv. output coding is twos complement binary with 1 lsb = fsr/4096. the ideal input/ output transfer function for the ad7864-1 is shown in table i. table i. ideal input/output code table for the ad7864-1 analog input 1 digital output code transition +fsr/2 C C C C C C C C C C C
ad7864 e10e rev. b ad7864-3 figure 4 shows the analog input section of the ad7864-3. the analog input range is 2.5 v on the v in1a input. the v in1b input can be left unconnected, but if it is connected to a poten- tial, that potential must be agnd. 2.5v reference t/h to adc reference circuitry 6k r2 to internal comparator ad7864-3 r1 v in1b v in1a v ref figure 4. ad7864-3 analog input structure for the ad7864-3, r1 = 6 k w and r2 = 6 k w. as a result, the v in1a input should be driven from a low impedance source. the resistor input stage is followed by the high input impedance stage of the track/hold amplifier. t he designed code transitions take place midway between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs, and so on) lsb size is given by the formula 1 lsb = fsr/ 4096. output coding is twos complement binary with 1 lsb = fsr/4096 = 5 v/4096 = 1.22 mv. the ideal input/output transfer function for the ad7864-3 is shown in table iii. table iii. ideal input/output code table for the ad7864-3 analog input l digital output code transition +fsr/2 C C C C C C C C C
ad7864 e11e rev. b timing and control r eading between each conversion in the conversion sequence figure 7 shows the timing and control sequence required to obtain the optimum throughput rate from the ad7864. to obtain the optimum throughput from the ad7864, the user must read the result of each conversion as it becomes available. the timing diagram in figure 7 shows a read operation each time the eoc signal goes logic low. the timing in figure 7 shows a conversion on all four analog channels (sl1 to sl4 = 1, see the c hannel selection section), thus there are four eoc pulses and four read operations to access the result of each of the four conversions. a conversion is initiated on the rising edge of convst . this places all four track/holds into hold simultaneously. new data from this conversion sequence is available for the first channel selected (v in1 ) 1.65 m s later. the conversion on each subse- quent channel is completed at 1.65 m s intervals. the end of each conversion is indicated by the falling edge of the eoc signal. the busy output signal indicates the end of conversion for all selected channels (four in this case). data is read from the part via a 12-bit parallel data bus with standard cs and rd signals. the cs and rd inputs are inter- nally gated to enable the conversion result onto the data bus. the data lines db0 to db11 leave their high impedance state when both cs and rd are logic low. therefore, cs m ay be permanently tied logic low and the rd signal used to access the conversion result. since each conversion result is latched into its output data register prior to eoc going logic low, another option is to tie the eoc and rd pins together and use the rising edge of eoc to latch the conversion result. although the ad7864 has some special features that permit reading dur- ing a conversion (e.g., a separate supply for the output data drivers, v drive ) for optimum performance it is recommended that the read operation be completed when eoc is logic low, i.e., before the start of the next conversion. although figure 8 shows the read operation taking place during the eoc pulse, a read operation can take place at any time. figure 8 shows a timing specification called quiet time. this is the amount of time that should be left after a read operation and before the next conversion is initiated. the quiet time depends heavily on data bus capacitance, but 50 ns to 100 ns is typical. the signal labeled frstdata (first data-word) indicates to the user that the pointer associated with the output data regis- ters is pointing to the first conversion result by going logic high. the pointer is reset to point to the first data location (i.e., first c onversion result,) at the end of the first conversion (frstdata logic high). the pointer is incremented to point to the next register (next conversion result) when that conversion result is available. thus, frstdata in figure 7 is seen to go low just prior to the second eoc pulse. repeated read operations during a conversion continues to access the d ata at the current pointer location until the pointer is incremented at the end of that conversion. note that frstdata has an indeterminate logic state after initial power-up. this means that for the first conver- sion sequence after power-up, the frstdata logic output may already be logic high before the end of the first conversion. this condition is indicated by the dashed line in figure 7. also the frstdata logic output may already be high as a result of the previous read sequence as is the case after the fourth read in figure 7. the fourth read (rising edge of rd ) resets the pointer to the first data location. therefore, frstdata is already high when the next conversion sequence is in itiated. see the accessing the output data registers section. t conv t busy quiet time t 1 t 8 t 12 t 3 t 4 t 5 t 6 t 7 v in1 v in2 v in3 v in4 100ns 100ns data convst busy eoc frstdata rd cs h /s sel sl1 to sl4 t 2 t conv t conv t conv t acq t 11 t 10 figure 7. timing diagram for reading during conversion
ad7864 e12e rev. b reading after the conversion sequence figure 8 shows the same conversion sequence as figure 7. in this case, however, the results of the four conversions (on v in1 to v in4 ) are read after all conversions have finished, i.e., when busy goes logic low. the frstdata signal goes logic high at the end of the first conversion just prior to eoc going logic low. as mentioned previously, frstdata has an indetermi- nate state after initial power-up, therefore frstdata may already be logic high. unlike the case when reading between each conversion, the output data register pointer is incremented on the rising edge of rd because the next conversion result is available. this means frstdata will go logic low after the first rising edge on rd . successive read operations will access the remaining conversion results in an ascending channel order. each read operation increments the output data register pointer. the read operation that accesses the last conversion result causes the output data register pointer to be reset so that the next read operation will access the first conv ersion result again. this is shown in figure 8 with the fifth read after busy goes low accessing the result of the conversion on v in1 . thus the output data registers act as a circular buffer in which the conversion results may be continu- ally accessed. the frstdata signal will go high when the first conversion result is available. data is enabled onto the data bus db0 to db11 using cs and rd . both cs and rd have the same functionality as described in the previous section. there are no restrictions or perfor- mance implications associated with the position of the read operations after busy goes low. the only restriction is that there is minimum time between read operations. notice also that the quiet time must be allowed before the start of the next conversion. using an external clock the logic input int /ext clk allows the user to operate the ad7864 using the internal clock oscillator or an external clock. the optimum performance is achieved by using the internal clock on the ad7864. the highest external clock frequency allowed is 5 mhz. this means a conversion time of 2.6 m s compared to 1.65 m s using the internal clock. in some instances, however, it may be useful to use an external clock when high throughput rates are not required. for example, two or more ad7864s may be synchronized by using the same external clock for all devices. in this way, there is no latency between output logic signals like eoc due to differences in the frequency of the internal clock oscillators. figure 9 shows how the various logic outputs are synchronized to the clk signal. each conversion requires 14 clocks. the output data register pointer is reset to point to the first register location on the falling edge of the 12th clock cycle of the first conversion in the conversion sequence
ad7864 e13e rev. b convst busy eoc rd 1 23 4567891011121314 1 234567 8910 11 12 13 14 1 21314 clk frstdata first conversion complete last conversion complete figure 9. using an external clock standby mode operation the ad7864 has a standby mode whereby the device can be placed in a low current consumption mode (5 m a typ). the ad7864 is placed in standby by bringing the logic input stby low. the ad7864 can be powered up again for normal opera- tion by bringing stby logic high. the output data buffers are still operational while the ad7864 is in standby. this means the user can still continue to access the conversion results while the ad7864 is in standby. this feature can be used to reduce the average power consumption in a system using low through- p ut rates. to reduce average power consumption, the ad7864 c an be placed in standby at the end of each conversion sequence, i.e., when busy goes low and is taken out of standby again prior to the start of the next conversion sequence. the time it takes the ad7864 to come out of standby is called the wake-up time. this wake-up time limits the maximum throughput rate at which the ad7864 can be operated when powering down between conversion sequences. the ad7864 wakes up in approximately 2 m s when using an external reference. the wake-up time is also 2 m s when the standby time is less than 1 ms while using the internal reference. figure 11 shows the wake-up time of the ad7864 for standby times greater than 1 ms. note that when the ad7864 is left in standby for periods of time greater than 1 ms, the part will require more than 2 m s to wake up. for example, after initial power-up, using the internal reference the ad7864 takes 6 ms to power up. the maximum throughput rate that can be achieved when powering down between conversions is 1/(t busy + 2 m s) = 100 ksps, approxi- mately. when operating the ad7864 in a standby mode between conversions, the power savings can be significant. for example, with a throughput rate of 10 ksps, the ad7864 is powered down (i dd = 5 m a) for 90 m s out of every 100 m s (see figure 10). therefore, the average power consumption drops to 125/10 mw or 12.5 mw approximately. standby time (sec) 1.0 0.9 0 0.0001 10 0.001 0.01 0.1 1 0.6 0.3 0.2 0.1 0.8 0.7 0.4 0.5 power-up time (ms) +105 c +25 c e40 c figure 11. power-up time vs. standby time using the on-chip reference (decoupled with 0.1 m f capacitor) accessing the output data registers there are four output data registers, one for each of the four possible conversion results from a conversion sequence. the result of the first conversion in a conversion sequence is placed in register 1, the second result is placed in register 2, and so on. for example, if the conversion sequence v in1 , v in3 , and v in4 is selected (see the conversion sequence selection sec- tion), the results of the conversion on v in1 , v in3 , and v in4 are placed in registers 1 to 3, respectively. the output data register pointer is reset to point to register 1 at the end of the first con- version in the sequence, just prior to eoc going low. at this convst busy stby 100 s 7 s t busy i dd = 20 a t busy 2 s t wake-up figure 10. power-down between conversion sequences
ad7864 e14e rev. b point, the logic output frstdata goes logic high to indicate that the output data register pointer is addressing register 1. when cs and rd are both logic low, the contents of the addressed register are enabled onto the data bus (db0 to db11). when reading the output data registers after a conversion sequence, i.e., when busy goes low, the register pointer is incremented on the rising edge of the rd signal, as shown in figure 12. however, when reading the conversion results during the conversion sequence, the pointer is not incremented until a valid conversion result is in the register to be addressed. in this case, the pointer is incremented when the conversion has ended and the result has been transferred to the output data register. this happens just prior to eoc going low, therefore eoc may be used to enable the register contents onto the data bus, as described in the reading between each conversion in the conver- sion s equence section. the pointer is reset to point to register 1 on the rising edge of the rd signal when the last conversion result in the sequence is being read. in the example shown, this means that the pointer is set to register 1 when the contents of register 3 are read. db0 to db11 o/p drivers oe no. 1 not valid (v in3 ) (v in1 ) (v in4 ) oe no. 2 oe no. 3 oe no. 4 2-bit counter v drive oe rd cs reset decode output data registers * the pointer will not be incremented by a rising edge on rd until the conversion result is in the output data register. the pointer is reset when the last conversion result is read frstdata pointer * ad7864 figure 12. output data registers offset and full-scale adjustment in most digital signal processing (dsp) applications, offset and full-scale errors have little or no effect on system performance. offset error can always be eliminated in the analog domain by ac coupling. full-scale error effect is linear and does not cause problems as long as the input signal is within the full dynamic range of the adc. invariably, some applications require that the input signal spans the full analog input dynamic range. in such applications, offset and full-scale error have to be adjusted to zero. figure 13 shows a circuit that can be used to adjust the offset and full-scale errors on the ad7864 (v a1 on the ad7864-1 version is shown for example purposes only). where adjustment is required, offset error must be adjusted before full-scale error. this is achieved by trimming the offset of the op amp driving t he analog input of the ad7864 while the input voltage is 1/2 lsb below analog ground. the trim procedure is as follows: apply a voltage of C C C C C snr = (6.02 n + 1.76) db (1) where n is the number of bits. thus, for an ideal 12-bit converter, snr = 74 db. figure 14 shows a histogram plot for 8192 conversions of a dc input using the ad7864 with a 5 v supply. the analog input was set at the center of a code. it can be seen that all the codes appear in the one output bin, indicating very good noise perfor- mance from the adc.
ad7864 e15e rev. b adc code 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 9000 8000 0 4000 3000 2000 1000 6000 5000 7000 counts figure 14. histogram of 8192 conversions of a dc input the output spectrum from the adc is evaluated by applying a sine wave signal of very low distortion to the analog input. a fast fourier transform (fft) plot is generated from which the snr data can be o btained. figure 15 shows a typical 4096 point fft plot of the ad 7864 with an input signal of 99.9 khz and a sampling frequency of 500 khz. the snr obtained from this graph is 72.6 db. it should be noted that the harmonics are taken into account when calculating the snr. figure 15. fft plot effective number of bits the formula given in equation 1 relates the snr to the number of bits. rewriting the formula, as in equation 2, it is possible to get a measure of performance expressed in effective number of bits ( n ). n = snr C C C C
ad7864 e16e rev. b ac linearity plots the plots shown in figure 18 below show typical dnl and inl plots for the ad7864. 0 500 1000 1500 2000 2500 3000 3500 4000 3.00 2.00 1.00 0 e1.00 e2.00 e3.00 adc code dnl (lsb) e0.50 0 0.50 1.00 1.50 2.00 2.50 0 500 1000 1500 2000 2500 3000 3500 4000 adc code inl (lsb) e2.50 e2.00 e1.50 e1.00 figure 18. typical dnl and inl plots measuring aperture jitter a convenient way to measure aperture jitter is to use the rela- tionship it is known to have with snr (signal-to-noise plus distortion) given below: snr f jitter in = ? ? ? 20 log 2 10 1 () ps (3) where: snr j itter = signal-to-noise due to the rms time jitter s = rms time jitter. f in = sinusoidal input frequency (1 mhz in this case). from equation 3, it can be seen that the signal-to-noise ratio due to jitter degrades significantly with frequency. at low input frequencies, the measured snr performance of the ad7864 is indicative of noise performance due to quantization noise and system noise only (72 dbs used as a typical figure here). therefore, by measuring the overall snr performance (includ- ing noise due to jitter, system, and quantization) of the ad7864, a good estimation of the jitter performance of the ad7864 can be calculated. frequency (hz) 12 11 5 900000 1100000 950000 1000000 1050000 9 8 7 6 10 enob figure 19. enob of the ad7864 at 1 mhz from figure 19, the enob of the ad7864 at 1 mhz is ap proximately 11 bits. this is equivalent to 68 dbs snr. snr total = snr j itter + snr quant = 68 dbs 68 dbs = snr j itter + 72 dbs ( at 100 khz) snr j itter = 70.2 dbs from equation 3, 70.2 dbs = 20 log 10 [1/(2 1 mhz )] s = 49 ps where s is the rms jitter of the ad7864.
ad7864 e17e rev. b microprocessor interfacing the high speed parallel interface of the ad7864 allows easy interfacing to most dsps and microprocessors. this interface consists of the data lines (db0 to db11), cs , rd , wr , eoc , and busy. ad7864 to adsp-2100/adsp-2101/adsp-2102 interface figure 20 shows an interface between the ad7864 and the adsp-2100. the convst signal can be generated by the adsp-2100 or from some other external source. figure 20 shows the cs being generated by a combination of the dms signal and the address bus of the adsp-2100. in this way, the ad7864 is mapped i nto the data memory space of the adsp-2100. the ad7864 busy line provides an interrupt to the adsp- 2 100 when the conversion sequence is complete on all the selected channels. the conversion results can then be read from the ad7864 using successive read operations. alternately, one can use the eoc pulse to interrupt the adsp-2100 when the conversion on each channel is complete when reading between each conversion in the conversion sequence (figure 7). the ad7864 is read using the following instruction mr0 = dm(adc) where mr0 is the adsp-2100 mr0 register and adc is the ad7864 address. cs rd wr busy convst db0 to db11 ad7864 v in1 v in2 v in3 v in4 dt1/f0 irqn rd wr d0 to d24 dms a0 to a13 adsp-210x address decode figure 20. ad7864 to adsp-210x interface ad7864 to tms320c5x interface figure 21 shows an interface between the ad7864 and the tms320c5x. as with the previous interfaces, conversion can be initiated from the tms320c5x or from an external source, and the processor is interrupted when the conversion sequence is completed. the cs signal to the ad7864 is derived from the ds signal and a decode of the address bus. this maps the ad7864 into external data memory. the rd signal from the tms320c5x is used to enable the adc data onto the data bus. the ad7864 has a fast parallel bus so there are no wait state requirements. the following instruction is used to read the conversion results from the ad7864 in d,adc where d is the data memory address and adc is the ad7864 address. cs rd wr busy convst db0 to db11 ad7864 v in1 v in2 v in3 v in4 pa0 intn rd we d0 to d15 ds a0 to a13 tms320c5x address decode figure 21. ad7864 to tms320c5x interface ad7864 to mc68000 interface an interface between the ad7864 and the mc68000 is shown in figure 22. the conversion can be initiated from the mc68000 or from an external source. the ad7864 busy line can be used to interrupt the processor or, alternatively, software delays can ensure that the conversion has been completed before a read to the ad7864 is attempted. because of the nature of its inter- rupts, the mc68000 requires additional logic (not shown in figure 22) to allow it to be interrupted correctly. for further information on mc68000 interrupts, consult the mc68000 users manual. the mc68000 as and r/ w outputs are used to generate a separate rd input signal for the ad7864. rd is used to drive the mc68000 dtack input to allow the processor to execute a normal read operation to the ad7864. the conversion results are read using the following mc68000 instruction: move.w adc,d0 where d0 is the mc68000 d0 register and adc is the ad7864 address. cs rd convst db0 to db11 ad7864 v in1 v in2 v in3 v in4 dtack as d0 to d15 a0 to a15 mc68000 address decode clock r/ w figure 22. ad7864 to mc68000 interface
ad7864 e18e rev. b vector motor control the current drawn by a motor can be split into two components: one produces torque and the other produces magnetic flux. for optimal performance of the motor, these two components should be controlled independently. in conventional methods of controlling a 3-phase motor, the current (or voltage) supplied to the motor and the frequency of the drive are the basic control variables. however, both the torque and flux are functions of current (or voltage) and frequency. this coupling effect can reduce the performance of the motor because, for example, if the torque is increased by increasing the frequency, the flux tends to decrease. vector control of an ac motor involves controlling phase in addition to drive and current frequency. controlling the phase of the motor requires feedback information on the position of the rotor relative to the rotating magnetic field in the motor. using this information, a vector controller mathematically trans- forms the three phase drive currents into separate torque and flux components. the ad7864, with its 4-channel simultaneous sampling capability, is ideally suited for use in vector motor control applications. a block diagram of a vector motor control application using the ad7864 is shown in figure 23. the position of the field is derived by determining the current in each phase of the motor. only two phase currents need to be measured because the third can be calculated if two phases are known. v in1 and v in2 of the ad7864 are used to digitize this information. simultaneous sampling is critical to maintain the relative phase information between the two channels. a current sensing isola- tion amplifier, transformer, or hall effect sensor is used between the motor and the ad7864. rotor information is obtained by measuring the voltage from two of the inputs to the motor. v in3 and v in4 of the ad7864 are used to obtain this information. once again the relative phase of the two channels is important. a dsp microprocessor is used to perform the mathematical transformations and control loop calculations on the informa- tion fed back by the ad7864. multiple ad7864s in a system figure 24 shows a system where a number of ad7864s can be configured to handle multiple input channels. this type of con- figuration is common in applications such as sonar and radar. the ad7864 is specified with maximum limits on aperture delay match. this means that the user knows the difference in the sampling instant between all channels. this allows the user to maintain relative phase information between the differ- ent channels. the ad7864 has a maximum aperture delay matching of 4 ns. all ad7864s use the same external sar clock (5 mhz). therefore, the conversion time for all devices is the same and so all devices may be read simultaneously. in the example shown in figure 24, the data outputs of two ad7864s are enabled onto a 32-bit wide data bus when eoc goes low. eoc ad7864 v in1 v in2 v in3 v in4 address decode v ref clkin cs rd 12 32 ad7864 v in1 v in2 v in3 v in4 v ref clkin cs rd 12 adsp-2106x rd ref193 5mhz figure 24. multiple ad7864s in multichannel system dac torque and flux control loop calculations and two to three phase information dsp microprocessor dac dac drive circuitry 3- phase motor i c i b i a v b v a transformation to torque and flux current components + e + e ad7864 * v in1 v in2 v in3 v in4 isolation amplifiers voltage attenuators torque setpoint flux setpoint * additional pins omitted for clarity figure 23. vector motor control using the ad7864
ad7864 e19e rev. b outline dimensions 44-lead metric quad flat package [mqfp] (s-44-2) dimensions shown in millimeters 0.80 bsc 0.45 0.30 2.45 max 1.03 0.88 0.73 8 0.8 seating plane top view (pins down) 1 33 34 11 12 23 22 44 coplanarity 0.10 pin 1 0.25 min view a rotated 90 ccw 7 0 2.10 2.00 1.95 view a 13.90 bsc sq 10.00 bsc sq compliant to jedec standards mo-112-aa-1
e20e rev. b c01341e0e3/04(b) ad7864 revision history location page 3/04?data sheet changed from rev. a to rev. b. changes to specifications and to footnote 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to timing characteristics footnote 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 addition to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to figure 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 changes to figure 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 added revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 updated publication code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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